The invention relates generally to computer architecture and microprocessor design, and more specifically to bussing and bussing methods used to transfer data from one point to another.
The transfer of data from one point to another is a vital function of all computers and microprocessors. The structure by which data is transferred is known as a bus, and the method by which the data is transferred on the bus is known as the bussing scheme or bussing method.
There are many different types of busses and bussing schemes. Since the transfer of data is critical in processor performance, high-speed bussing has become vital. Unfortunately, high-speed bussing becomes very difficult as busses grow in length to accommodate larger and larger chip sizes, while the physical width of the bus becomes narrower to allow more devices to be placed on a unit of silicon. Longer busses result in increased data propagation delay across the bus due to increased RC (Resistance-Capacitance) loading on the bus.
One popular bussing scheme to overcome the difficulties of longer bus lengths is the differential bus scheme. A differential bus requires a true data signal and a complement data signal to complete a data transfer. The receiver in a differential bus design reacts to the voltage difference between the true and complementary bit lines. Reduced data transfer times in a differential bus design result primarily from the limited voltage swings needed on the true and differential bit lines. Typical differentials required for reliable operation of the differential bus range from 100 mV to 300 mV. Before a transfer of data across the differential bus, both lines are pre-charged, or biased, to some level above ground, typically Vdd/2, where Vdd is the power supply voltage in the design. As data is driven onto the bus, one of the bit line""s potential is pulled towards Vdd and the other bit line""s potential is discharged towards ground. For example if the power supply voltage is 3V, the bias level on the differential bit lines will be 1.5V. If the data transitions from ground to Vdd (3V in this example), the potential on the true bit line increases to 2.0V and the potential on the complementary bit line decreases to 1.0V, thereby resulting in a voltage differential of 1V.
While this differential bussing scheme works well, there are still some drawbacks. It requires special biasing circuitry. For CMOS implementations, biasing at a level other than ground or Vdd results in static power dissipation. Biasing at a level between ground and Vdd may require an additional reference power supply and may require an additional clock cycle, thereby adding to the latency of the data transfer which also means reduced bandwidth on the bus.
Accordingly, there is a need to design a faster bussing scheme.
The present invention discloses a processor having a differential bus, comprising: a differential bus; and a clock line carrying a clock signal that determines a pre-charge time of the differential bus. The differential signals are pre-charged by distributed devices to Vdd at every transmitter location along the bus. This reduces the pre-charge time on the heavily loaded busses, thereby apportioning a larger amount of the clock cycle time towards evaluation, i.e. the development of a voltage differential on the true and complement bits of the bus. A self-tracking clock is used to generate the pre-charge and evaluation phases from a standard clock.
Advantageously, the present invention provides the following advantages: ensures complete pre-charge to Vdd for the differential bit lines, across process, voltage and temperature variations, allocates sufficient pre-charge time that is needed to complete the pre-charge operation, thereby maximizing the evaluation time. In addition, the differential bit lines are pre-charged to Vdd, thereby eliminating the need to have special biasing circuitry, preventing any static power dissipation in this design. The pre-charge scheme further provides distributed pre-charge devices and a self-tracking clock to regulate the pre-charge time and does not add to the latency of the differential bus, thereby permitting back-to-back accesses on the bus, resulting in higher data transfer bandwidth.